The present invention relates to very large scale semiconductor integrated (VLSI) circuits and technology, and more particularly relates to an economical binary technique for arbitrary array line depth decoding using back-gate CMOS devices, e.g., NFET devices, arranged in a decode personalization circuit to replace conventional binary tree decodes normally included in word line depth decoding circuitry to save power and IC area when implemented in SRAM, DRAM, ROM, ROS and other memory storage devices.
The need for low-power VLSI circuitry for use in numerous electronic applications is ever-growing. To reduce power consumption, lower operating voltages (Vdd) and minimized device dimensions are the constant aim of IC designers. To lower the threshold voltage (VTh) and the operational voltage for IC devices, silicon-on-oxide (SOI) MOSFETs with body contact or back-gates, bulk MOSFETs with isolated body, and like devices have been developed and are known. Fuse, et al., “0.5 V SOI CMOS Pass-Gate Logic,” DIGEST OF TECHNICAL PAPERS, IEEE International Solid-State Circuits Conference; vol. 39, February 1996; pp. 88-89 is a good example.
SOI metal oxide field effect transistors (MOSFETs) can be fabricated into two distinct modes of operation: 1) fully depleted (FD), and 2) partially depleted (PD) channel region (i.e., body). In conventional fully-depleted SOI devices, the silicon film thickness is usually less than or equal to half the depletion width of the bulk device. The surface potentials at the front and back interfaces are strongly coupled to each other and capacitively coupled to the front-gate and substrate through the front-gate dielectric and the buried oxide, respectively. Therefore, the potential throughout the silicon film, and hence the charge, is determined by the bias conditions on both the front-gate and the substrate. By using the substrate as a back-gate, the device can be operated as a dual-gated device. A back-gate may or may not have a discrete gate plate, which is physically insulated from the conduction layer. Devices may be back-gated by merely contacting the device body.
Dynamic threshold metal oxide semiconductor (DTMOS) devices can be fabricated on silicon-on insulator (SOI) substrates as described, for example, in U.S. Pat. No. 5,559,368, to Hu, et al., issued Sep. 24, 1996, and incorporated by reference (“the '368 patent”). The '368 patent discloses a DTMOS device (MOSFET) fabricated on a silicon-on-insulator substrate to include a four-terminal layout comprising source, drain, gate and body contacts. The DTMOS device comprises a substrate with a buried oxide layer formed therein, and a P—SI film disposed on the oxide layer. N+ sources and drains are formed in the film. A gate electrode is formed on a gate insulation layer on the film between the source and drain of the MOSFET device. The gate and film are interconnected (gate to body) to reduce the turn-on voltage (VTh) when the gate voltage is high, and elevate it when the gate voltage is low.
The reduced threshold or turn-on voltage (VTh) improves MOSFET device performance in numerous respects. When the FET is OFF, the threshold voltage is increased, reducing sub-threshold leakage currents. Applications that use DTCMOS devices realize lower leakage currents while the MOSFET device is off, and higher drive currents when the device is on. In non-DTCMOS structures, the bulk silicon material from which the channel of the MOSFET device is formed is either grounded, or in many applications connected to the source region of the device.
U.S. Pat. No. 6,326,666, to Bernstein, et al., issued Dec. 4, 2001, and incorporated by reference (the '666 patent), discloses a DTCMOS circuit implemented in SOI that includes a plurality of input transistors with threshold voltages controlled by early arriving logic signals. The DTCMOS transistors have body contacts connected to the monocrystalline silicon film of the device. Use is made of the body contact for controlling the voltage threshold (VTh) of a device that receives a respective logic signal. Earlier arriving logic signals are coupled to the gate of one input transistor, as well as to the body contact of another transistor receiving a later arriving logic signal. A data transition on the earlier arriving logic signal will lower the voltage threshold of the input transistor receiving the later arriving signal. Thus, a dynamic lowering of the voltage threshold occurs, permitting an increase in speed for the logic circuit.
U.S. Pat. No. 6,462,585, to Bernstein, et al., issued Oct. 8, 2002, and incorporated by reference (“the '585 patent”), discloses an asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) device that includes a cross-coupled latch circuit to improve effective Vdd/VTh. The cross-coupled latch circuit substantially reduces body-to-source/drain parasitic capacitances as well as structural body resistance parasitics of the asymmetric-DGCMOS device and improves the effective Vdd/VTh ratio without causing any substantial body-to-source/drain parasitic capacitances or structural body resistance parasitics. DGCMOS devices are scalable below about 0.1 mm, while able to operate at voltages below about 1 V.
Back-gate devices are known to be used in semiconductor memory circuits and devices such as dynamic random access memory (DRAM), static random access memory (SRAM), video random access memory (VRAM), erasable programmable read only memory (EPROM), flash memory, etc. Memory devices, or cells, are generally located at intersections of word lines and bit lines (rows and columns of an array), where each cell conventionally stores a single bit of data as a logical “1” or a logical “0,” which may thereafter be individually accessed, addressed or selected. Each cell is addressed using two multi-bit numbers in some kind of decoder. The first multi-bit number, or row address, identifies the row of the memory array in which the memory cell is located. The second multi-bit number, or column address, identifies the column of the memory array in which the desired memory cell is located.
Back-gate device operation in such memory storage devices and the address encoders/decoders operating with them complement known techniques for interrogating memory arrays comprising individual storage elements and devices. Back-gate memory cells may comprise, for example, a string of field effect transistor (FET) switches that form a series connection to ground from a signal line. By use of back gating, a discharge path from a signal line may be influenced by precharging the signal line.
Japanese Patent No. JP 2000195276 to Morishima, published Jul. 14, 2000, discloses a memory decode circuit or tree that includes a voltage-controlled array decode tree circuit 80. The array decode tree circuit 80 includes NFET devices with their bodies tied to their source terminal as found in the conventional arts. The NFET devices are not arranged in the Morishima array decode tree circuit 80 to utilize the body effect. The array decode tree circuit 80 receives column address decoded from column address signal Y, and generates and outputs control signals BBL1, BBL2, so that BBL1 and BBL2 can control the level of the signals applied to devices comprising the memory cells (M). The body-biased NFET devices are controlled to be at a −Vpp potential level when corresponding column selection signals are off. The signals have a corresponding ground state when active. Morishima, however, does not suggest the use of coupled back-gate operation, nor does it suggest or teach using body voltage modulation to personalize the decode.
What would be desirable, therefore, in the field of semiconductor memory circuits and their operation is a decode personalization and like circuit constructed with back-gate MOSFET devices. In coupled back-gate operation, these devices positively capture logic states, reduce leakage currents and improve noise immunity by dynamically modulating threshold voltages during normal device operation. Such decode personalization would be particularly effective in SRAM, DRAM, ROM, ROS and other memory storage circuits in realizing significant reductions in leakage current (power) and chip area required to perform decode personalization.